受某知名半导体公司委托招聘:Senior/Engineer Design for Testability Engineering for Digital and Mixed Signal Communication Ics Division: Research & Development 工作地点：新加坡 职位职责： -Definition / generation of Design-for-Testability concept, ensure testability (DFT) and analyzability (DFA) of VLSI communication devices. -Development, implementation and verification of DFT / DFA measures (standard DFT measures as well as project specific non standard DFT measures). -Test mode definition / documentation / implementation / verification. -Test pattern generation / verification. -Responsibility for achievement of target structural test coverage. -Development of new DFT methods / features. -Increase DFT knowledge base, drive know-how exchange across projects and other locations. 职位要求： -Masters/Bachelor Degree in Electrical/Electronics Engineering. -Minimum of 3 years of working experience in DFT engineering. -Good knowledge in Boundary Scan, ATPG Scan, and MBIST is a must. -Working experience with industry standard tools like Fast Scan, EDT, DF advisor, DFT Compiler is an added advantage. -Knowledge in complete design flow is desired. -Proficiency in VHDL/Verilog is desired. -Proficient in high level programming languages “C”, “C++”, Perl and script writing. -Experience in Test development and Product engineering will be an added advantage. -A team player with an open and co-operative personality. Good communication, analytical and problem-solving skills.
